Reducing power consumption on a chip is desirable, especially when the chip is in a battery-powered mobile device. The chip typically has a system implemented thereon, and thus, is commonly referred to as a system on a chip (“SoC”). Contributors to power consumption in the SoC include dynamic power of various components within the SoC due to switching of transistors on the chip, and leakage power due to current leakage of transistors on the chip. Among the components in the SoC, central processing units (CPUs), which may be referred to as processing cores or processors, tend to consume a significant portion of the power.
To conserve power, a CPU that is not currently active may be placed in one of multiple low power modes. One conventional low power mode is implemented entirely within a CPU. In such a low power mode, the clock signal to the CPU is gated to reduce dynamic power of the CPU. This mode is useful when the CPU is not expected to perform operations. By gating the clock signal, transistors and various components within the CPU should not switch or change state unnecessarily. However, the CPU still exhibits significant power leakage because the CPU is still receiving power during such low power mode and current leaks through transistors within the CPU.
Additional power saving measures may be taken by resources outside of the CPU in some other the conventional low power modes. These additional power saving measures are typically implemented using software and/or firmware. One drawback of such measures is the latency at entry and/or exit of these low power modes. Thus, there is a need in the industry for low power modes that do not sacrifice latency for power saving.